RF transceivers that may be reconfigured and/or programmed have been sought after for many years. Conventionally, several radios for different applications were put together to provide a solution with some limited configurability. However, such architectures do not offer upgradability, because adding support for different frequencies requires significant radio redesign. A common platform is preferred to process all wireless signals if it can offer small form factor, low cost and low power consumption. Further, it is preferable to have a radio that can be configured to support different applications within a micro second. These features are not supported by the prior art.
J. L. Shanton in “A software defined radio transformation,” IEEE Military Communication Conference, pp. 1-5, 2009 describes a software defined radio architecture, which extends existing high frequency/very high frequency/ultrahigh frequency (HF/VHF/UHF) radio functions. However, the disclosed radio mainly works in low frequency and does not address high frequency band.
J. Craninckx, et al in “A fully configurable software-defined radio transceiver in 0.13 μm CMOS,” IEEE ISSCC, pp. 346-607, 2007 describe a software defined radio that can support 1-5 GHz RF signal processing with a configurable baseband bandwidth from 0.35 MHz to 23 MHz for receiving and 1 to 16 MHz for transmitting, as shown in FIG. 1A. Craninckx does not disclose the application switching speed; however, based upon the local oscillator (LO) generation architecture used by Craninckx, as shown in FIG. 1B, the switching time is expected to be as long as tens of micro seconds, because the LO switching is governed by a limited loop bandwidth, which requires a long settling time.
I. Hatai, I. Chakrabarti in “A high-speed, ROM-less DDFS for software defined radio system,” IEEE International Conference on Communication Control and Computing Technologies, pp. 115-119, 2010 disclosed using a Direct Digital Synthesizer (DDS) as a LO, as shown in FIG. 2, for a software defined radio, in order to provide a very fast channel switching time. However, such configurations are often constrained by the low output frequency of the synthesized clock, which is normally a fraction of the input clock frequency, which suggests a very high frequency operation of the DDS to support a wide band radio. However, such very high frequency operation would result in excessive power consumption. Also problematic are spurs of the DDS, which could be as high as −40 dBc for a high frequency output.
In the prior art, as advanced digital integrated circuit technologies arrived, people tried to direct digitize the incoming signal from the front low noise amplifier (LNA) and perform signal processing in the digital domain with enormous flexibility.
D. Agarwal, C. R. Anderson, and P. M. Athanas in “An 8 GHz ultra wideband transceiver prototyping testbed,” IEEE International workshop on Rapid System Prototyping, pp. 121-127, 2005 disclose a testbed with such an architecture, as shown in FIG. 3. This architecture uses several high-speed analog to digital converters (ADCs) to perform interleaved sampling at a high aggregate rate; however, the actual processing signal bandwidth is constrained by each ADC performance. Many other attempts have also used a similar architecture. Though this architecture can provide fast channel switching, it imposes a very high dynamic range requirement on the ADCs due to the concurrent wideband processing. Therefore, the associated power consumption is extremely high, which makes the architecture difficult to integrate into some applications. In particular, this architecture's power consumption will increase drastically with a wider signal bandwidth, so the architecture is difficult to use for ultra wide band applications.
R. Bagheri, A. Mirzaei, S. Chehrazi, M. E. Heidari, Minjae Lee, M. Mikhemar, Wai Tang, and A. A. Abidi in “An 800-MHz-6-GHz software defined wireless receiver in 90-nm CMOS,” IEEE JSSC, vol. 41, No. 12, pp. 2860-2876, 2006 describe a software defined radio receiver from a low power anti-aliasing filter perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete time analog filters, as shown in FIG. 4. The radio receiver disclosed has a wideband RF frontend with a low noise amplifier and a wide tuning range synthesizer spanning over 800 MHz to 6 GHz to cover the desired band. Owing to its narrow band signal processing, the receiver achieves low power consumption, which is on the same order of other customized radio receivers. However, its discrete filtering scheme inevitably introduces the spurs due to a switching clock. Also its frequency synthesizer does not provide fast channel switching, but rather has a switching time longer than tens of micro second.
K. Koli, S. Kallioinen, J. Jussila, P. Sivonen, and A. Parssinen, “A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS,” IEEE JSSC, vol. 45, No. 12, pp. 2807-2818, December 2010 disclose a direct delta-sigma receiver architecture based upon direct down-conversion, delta-sigma feedback that is up-converted to RF, and an N-path filtering technique, as shown in FIG. 5. This design processes the signal in a narrow band and exploits delta sigma modulation to achieve both excellent Signal to Noise-plus-Distortion Ratio (SNDR) and low power consumption. However, this architecture relies on an LO to configure the circuit center frequency, therefore the architecture does not provide fast channel switching.
N. Beilleau, H. Aboushady, F. Montaudon, and A. Cathelin in “A 1.3V 26 mV 3.2 GS/s undersampled LC bandpass ΣΔ ADC for a SDR ISM-band receiver in 130 nm CMOS,” IEEE RFIC, pp. 383-386, 2009 disclose an under-sampled LC bandpass ΣΔ modulator to directly convert the signal from the low noise amplifier (LNA) into digital data. This design achieves low power consumption and decent signal SNDR due to narrow band processing and use of a ΣΔ algorithm. However, this design, as shown in FIG. 6, lacks frequency tunability and is not able to process a very wide RF frequency.
What is needed is a radio architecture that is able to provide fast channel switching and cover a wide band without consuming significant amounts of power. The embodiments of the present disclosure answer these and other needs.